Electrically erasable and programmable memory devices, such as EEPROM and flash EEPROM, must handle and control relatively high internal voltages, assuring at the same time a high degree of stability. In order to accomplish a programming or an erasing operation, a voltage of 12 V or morn must be supplied to the memory cells.
It is therefore advisable to provide such devices with integrated components suitable to both limit any possible overvoltage, which could damage the memory cells or the circuitry connected to them, and stabilize internal voltages against temperature variations and statistical distribution of the process parameters. These components become essential for memory devices belonging to particular logic families, such as 5 V-only devices, wherein the voltage necessary for programming and erasing the memory cells is generated internally.
Integrated voltage limiters are commonly obtained in MOS devices by means of chains of reverse-biased planar junction diodes or diode-connected MOS transistors. Both these solutions have drawbacks. In the case of a chain of reverse-biased junction diodes, the overall clamping voltage, even if it shows a small dependence on the temperature and on the process parameters, is affected by a decrease with tune due to the injection of charge in the oxide layer covering the junction surface (walk-out phenomenon). In the case of a chain of diode-connected MOS transistors, instead, the overall clamping voltage depends on both the temperature and the variations of the process parameters due to their statistical distribution.
European Patent Application No. 0426241 describes a process for the manufacture of a zener diode to limit and stabilize the programming voltage supplied to EEPROM memory cells, suitable to be integrated with the EEPROM memory cells in a single chip. However, the process does not involve additional steps with respect to those usually necessary for the accomplishment of EEPROM memory cells. The junction subjected to break down is constituted by a P+region, with a dopant concentration of 10.sup.20 atoms/cm.sup.3 obtained in a process step corresponding to the implantation of source and drain areas of the P-channel transistors, and by an N- region, with a dopant concentration of 10.sup.19 atoms/cm.sup.3 obtained in a process step corresponding to the implantation of condensers of the EEPROM cells. This last step requires a lithographic mask, and is performed before the gate oxide layer is formed.
Because the manufacture of EEPROM and flash EEPROM memory devices involves different fabrication processes, the integration of the zener diode described in the cited Patent Application in a flash EEPROM memory device requires additional process steps with respect to those usually necessary for the accomplishment of a flash EEPROM, namely the step of implantation of condensers.